CS302 Assignment No. 3 Announced

Assignment No. 03
Semester: Spring 2011
CS302: Digital Logic Design


Total Marks: 10
Due Date: 08/06/2011


Instructions:
Please read the following instructions carefully before submitting assignment:
It should be clear that your assignment will not get any credit if:


 The assignment is submitted after due date.
 The assignment is submitted via email.
 The submitted assignment does not open or file is corrupt.
 All types of plagiarism are strictly prohibited. 


Objectives:


This assignment has been designed to enable you to understand the concepts of:


• Flip-Flops
• Flip-flops with asynchronous inputs
• Counters


Guidelines:


• Perform/write all steps while solving the problems.

Question No. 1                                                                                                    [Marks: 7]

Determine Q output waveform for a negative edge triggered J-K flip-flop with preset, clear and J, K inputs. You are required to draw Q output waveform on timing diagram.

Question No. 2                                                                                                    [Marks: 1+2]

Provide to-the-point answers to the following questions:

a)      How does a synchronous counter differ from asynchronous counter?

b)      How many states does a mod-12 counter have? What is minimum number of flip-flops required?

Note: You can use Microsoft Paint or MS Visio to draw output waveform.